Current communication standards are well settled for protocols such as 10 Gb/s Ethernet, 10 Gb/s SONET/SDH, and 40 Gb/s SONET/SDH. However, continuing rapid growth in network bandwidth requirements is pushing standards bodies, such as the Institute of Electrical and Electronics Engineers (IEEE) and International Telecommunication Union-Telecommunication (ITU-T), to start considering higher data rates. For example, recent standards activity has been focused on developing a 100 Gb/s Ethernet protocol.
As protocols move beyond 10 Gb/s and 40 Gb/s, network bandwidth requirements are starting to outstrip the capability of serial electronics and optics. Accordingly, network equipment is moving towards parallel configurations for delivering these higher data rates. This is a phenomenon similar to the current state of microprocessor central processing units (CPUs), where the CPU clock speed has been roughly constant for approximately the past five years, while at the same time CPU architecture has shifted to multi-core approaches to meet increasing computational demands.
Similarly, current 100 Gb/s Ethernet proposals for client-side interface interconnects are concentrated on some combination of parallel configurations. For example, combinations including 10×10 Gb/s, 5×20 Gb/s, and 4×25 Gb/s are under consideration. Similarly, network-side wavelength division multiplexed (WDM) interfaces above 40 Gb/s are quite difficult to realize in a fully serial fashion due to limitations associated with conventional optics and electronics. Accordingly, it is advantageous to implement network-side interfaces with reduced requirements on the electronics and optics bandwidth. It would be further advantageous to leverage the same or largely similar electronic components for both client-side and network line-side interfaces. Advantageously, Non-Recurring Engineering (NRE) costs could decrease, while part production volumes could increase accordingly.
Specifically, one of the critical system components in high-speed communication systems is an electronic serializer/deserializer (SERDES) circuit. SERDES circuits generally provide multiplexing (serializing) and de-multiplexing (de-serializing) of data signals to allow electronics to process high-speed data signals at a lower rate. The serializer (SER) part provides a low-speed parallel interface to the electronics, and multiplexes the data signals to output a drive signal to an optical interface. The deserializer (DES) part accepts signals from the optical interface, recovers the signal clock and data, and provides re-timed and parallel-de-multiplexed data to subsequent electronics.
Conventionally, what exists today are SERDES circuits that recover non-return-to-zero (NRZ) format incoming data, provide dual input/output (I/O) channels (such as for I and Q channels in Differential Quadrature Phase Shift Keying (DQPSK)), provide selectable rates between non-forward error correction (FEC) client rates of ˜20 Gb/s and FEC-encoded line rates of ˜22 Gb/s (i.e., total throughput of 40 Gb/s data, 44 Gb/s including FEC overhead), and provide standards-compliant SERDES Framer Interface Level 5 (SFI-5). SFI-5 is defined in OIF-SFI5-01.02, “Serdes Framer Interface Level 5 (SFI-5): Implementation Agreement for 40 Gb/s Interface for Physical Layer Devices” from the Optical Internetworking Forum (OIF), and the contents of which are incorporated in full by reference herein. Note, the SFI-5 standards specify maximum throughput rate of 50 Gb/s.
High-speed data signals are moving towards Return-to-Zero (RZ) formats for transmission. For example, DQPSK modulation format can be utilized with RZ optical pulses. Disadvantageously, conventional SERDES do not exist with functionality to recover clocks from RZ pulses. Additionally, 100 Gb/s data rates require a maximum throughput in excess of 50 Gb/s (the current maximum throughput of SFI-5). Thus, there exists a need for an overclocked SFI-5 interface to support rates in excess of 50 Gb/s as is required with framing and FEC for a 100 Gb/s signal. Further, conventional SERDES lack functionality required for high-speed data rates, such as differential coding support (e.g., DQPSK preceding), electronic pre-emphasis, receiver-side electronic dispersion compensation, and the like.
Thus, there exists a need for a SERDES circuit which can be extended to cover the requirements of both client and network-side interfaces in emerging high-speed (e.g., 100 Gb/s) communication networks.